/* VHDLOUT (GED) -- VHDL Netlist Data Output */
/* VHDLOUT (GED) -- VHDL Netzlistenausgabe */
/*
// Copyright (c) 2007-2012 Oliver Bartels F+E, Muenchen
// Author: Roman Ludwig
// Changes History:
//	rl (120427) RELEASED FOR BAE V7.8.
//	rl (101019) RELEASED FOR BAE V7.6.
//	rl (091021) RELEASED FOR BAE V7.4.
//	rl (081014) RELEASED FOR BAE V7.2.
//	rl (071029) RELEASED FOR BAE V7.0.
//	rl (070227) ORIGINAL CODING. DERIVED FROM EDIFOUT.ULC.
//
// DESCRIPTION
//
// The vhdlout User Language program generates a VHDL
// netlist output for use with external PLD layout/fitter programs.
// vhdlout reads a (logical *_log) netlist and automatically creates
// a layout worksheet to extract the required data.
// In hierachic design the VHDL netlist contains module ports
// The output is directed to a file with extension ".vhdl".
*/

// Includes
#include "pop.ulh"			// User Language popup utilities

// Disable undo state request
#pragma ULCALLERNOUNDO

// Messages
string UPRDDBFILE	= M("Jobdatei ? ","Job File ? ");
string REPSTART		= M("VHDL-Netzlisten Ausgabe...",
			    "VHDL netlist output...");
string REPDONE		= M("VHDL-Netzliste ausgegeben auf Datei '%s'.",
			    "VHDL netlist written to file '%s'.");
string ERRDDBACC	= M("Fehler beim Lesen der Design Datenbank!",
			    "Error reading design database!");

// INI file parameter name definitions
#define PAR_VHDLFEXT	"VHFLFEXT_GED"		// VHDL file name extension
#define PAR_VHDLEXTL	"VHFLEXTL_GED"		// External library name
#define PAR_EDFOPPATT	"EDFOPPATT_GED"		// Port net name pattern
#define PAR_EDFOPINDIR	"EDFOPINDIR_GED"	// Pin direction attr. name

// Global constants
string VHDLEXT = bae_inistrval(PAR_VHDLFEXT,".vhd")
					/* VHDL file name extension */;
string EXTLIBNAME = bae_inistrval(PAR_VHDLEXTL,"")
					/* External library name */;
string PORTPATT = bae_inistrval(PAR_EDFOPPATT,"[??]*")
					/* Port net name pattern */;
string PINDIRATT = bae_inistrval(PAR_EDFOPINDIR,"$dir")
					/* Pin direction attribute name */;

// Global variables
int nlfile				/* Netlist file handle */;

struct logpdef {			// Logical part definition
	string llname			/* Logical library part name */;
	STRINGS inpl			/* Input pin list */;
	int inpn			/* Input pin count */;
	STRINGS outl			/* Outut pin list */;
	int outn			/* Outut pin count */;
	STRINGS iol			/* Input/output pin list */;
	int ion				/* Input/output pin count */;
	index L_CPART cpart		/* Sample netlist part */;
	} lpartl[]			/* Logical library part list */;
int lpartn = 0				/* Logical library part count */;
int inslogidx				/* Logical lib. part insert index */;

// Main program
void main()
{
	string jobfname			/* Job file name */;
	string jobename			/* Job element name */;
	string placefname		/* Place file name */;
	string msgbuf			/* Message buffer */;
	// Perform BAE Demo check with abort option
	BAE_Demo_check(2);
	// Abort if invalid interpreter type
	if (uliptype()!=ULIPGED)
		error_class();
	// Get the plan file and element name
	if (bae_askddbfname(jobfname,1,UPRDDBFILE) ||
	 bae_askddbename(jobename,jobfname,DDBCLPCON,""))
		// Abort
		error_abort();
	// Build the VHDL netlist file name
	placefname=convstring(jobfname,0)+VHDLEXT;
	// Start output
	bae_prtdialog(REPSTART);
	// Open the VHDL netlist file
	nlfile=fopen(placefname,1);
	// Create the library worksheet
	switch (existddbelem(jobfname,DDBCLLAY,jobename)) {
		// Layout not found
		case 0 :
		createlay(jobfname,jobename);
		break;
		// Layout does already exist
		case 1 :
		bae_loadelem(jobfname,jobename,DDBCLLAY);
		break;
		// File access failed
		default :
		error(ERRDDBACC);
		}
	// Create the cell definition list
	creacelllist();
	// Write the design
	writedesign();
	// Write the output done message
	sprintf(msgbuf,REPDONE,placefname);
	bae_prtdialog(msgbuf);
}

static void createlay(string filename,string elemname)
/*
// Create the layout sheet for the netlist
// Parameters:
//	string filename		: Layout file name
//	string elemname		: Layout element name
*/
{
	// Insert the new element parameters
	bae_clriactqueue();
	bae_storemenuiact(1,0,LMB);
	bae_storetextiact(1,filename);
	bae_storetextiact(1,elemname);
	bae_storetextiact(1,"10");
	bae_storetextiact(1,"10");
	// Call the create new element menu function
	if (bae_callmenu(MNU_GEDCREELEM))
		// Parameter store failed
		error(ERRDDBACC);
}

static void creacelllist()
/*
// Create the logical cell library list
*/
{
	index L_CPART cpart		/* Connection part index */;
	index L_CPIN cpin		/* Connection pin index */;
	index L_ATTRIBUTE attr		/* Attribute index */;
	string logname			/* Logical library part name */;
	string pinname			/* Pin name */;
	string dirname			/* Direction name */;
	int inoutfound			/* INOUT pin found */;
	int outfound			/* OUTPUT pin found */;
	int i				/* Loop control variable */;
	forall (cpart) {
		// Get the logical library part name
		forall (attr of cpart where attr.NAME=="$llname") {
			// Store the logical library part name
			logname=attr.VALUE;
			strupper(logname);
			break;
			}
		// Update logical library part list
		fclogp(logname,cpart);
		}
	// Loop for all log. library parts
	for (i=0;i<lpartn;i++) {
		// Loop for all output pins
		cpart=lpartl[i].cpart;
		forall (cpin of cpart) {
			inoutfound=outfound=0;
			forall (attr of cpin where attr.NAME==PINDIRATT) {
				// Get the direction
				dirname=attr.VALUE;
				strupper(dirname);
				if (dirname=="INOUT")
					inoutfound=1;
				else if (dirname=="OUTPUT")
					outfound=1;
				break;
				}
			// Get the pin name
			pinname=cpin.NAME;
			if (inoutfound) {
				lpartl[i].iol[lpartl[i].ion]=pinname;
				lpartl[i].ion++;
				}
			else if (outfound) {
				lpartl[i].outl[lpartl[i].outn]=pinname;
				lpartl[i].outn++;
				}
			else {
				lpartl[i].inpl[lpartl[i].inpn]=pinname;
				lpartl[i].inpn++;
				}
			}
		}
}

static void fclogp(string llname,index L_CPART cpart)
/*
// Find or create a logical library part name entry
*/
{
	int logidx			/* Cur. log. part index */;
	int i				/* Loop control variable */;
	// Test if this log. part exists
	if ((logidx=findlog(llname))>=0)
		// Log. library part exists
		return;
	// Allocate new log. part entry
	lpartn++;
	// Copy old data entries to new position
	for (i=(lpartn-1)-1;i>=inslogidx;i--)
		lpartl[i+1]=lpartl[i];
	// Insert new data
	lpartl[inslogidx].llname=llname;
	lpartl[inslogidx].cpart=cpart;
	lpartl[inslogidx].inpn=0;
	lpartl[inslogidx].outn=0;
	lpartl[inslogidx].ion=0;
}

static int findlog(string llname)
/*
// Search a log. part entry
// Return value :
//	log. part index or (-1) if not of found
// Parameters :
//	string log. part	: Name of log. part searched
*/
{
	int slb=0			/* Search lower boundary */;
	int sub=lpartn-1		/* Search upper boundary */;
	int sidx			/* Search index */;
	int compres			/* Compare result */;
	// Loop until search area empty
	while (slb<=sub) {
		// Get the search index
		sidx=(slb+sub)>>1;
		// Compare entries
		compres=strcmp(llname,lpartl[sidx].llname);
		// Test if log. part found
		if (compres==0)
			// Log. part found
			return(sidx);
		// Update the search area
		if (compres<0)
			sub=sidx-1;
		else
			slb=sidx+1;
		}
	// Store the insert log. part index
	inslogidx=slb;
	// Log. part not found
	return(-1);
}

static void writedesign()
/*
// Write the design
*/
{
	index L_CPART cpart		/* Connection part index */;
	index L_CPIN cpin		/* Connection pin index */;
	index L_CNET cnet		/* Connection list index */;
	index L_ATTRIBUTE attr		/* Attribute index */;
	string jobname			/* Job name */;
	string netname			/* Net name */;
	string partname			/* Part name */;
	string logname			/* Logical library part name */;
	string dirname			/* Direction name */;
	int inoutfound			/* INOUT pin found */;
	int outfound			/* OUTPUT pin found */;
	STRINGS inpl			/* Input pin list */;
	int inpn = 0			/* Input pin count */;
	STRINGS outl			/* Outut pin list */;
	int outn = 0			/* Outut pin count */;
	STRINGS iol			/* Input/output pin list */;
	int ion = 0			/* Input/output pin count */;
	int listflag = 0		/* List output flag */;
	int i, j			/* Loop control variables */;
	// Get the job name
	jobname=bae_planename();
	strupper(jobname);
	// Write the library reference
	fprintf(nlfile,"-- Bartels AutoEngineer %s, VHDL netlist output\n",
	 bae_swversion(0));
	fprintf(nlfile,"\n-- Project file :%s\n",bae_planfname());
	fprintf(nlfile,"\n-- Output time %s\n\n",getdatetime());
	fprintf(nlfile,"LIBRARY IEEE;\n");
	fprintf(nlfile,"USE IEEE.STD_LOGIC_1164.ALL;\n");
	fprintf(nlfile,"USE IEEE.STD_LOGIC_UNSIGNED.ALL;\n");
	fprintf(nlfile,"LIBRARY WORK;\n");
	fprintf(nlfile,"USE WORK.MESSAGES.ALL;\n");
	if (EXTLIBNAME!="")
		fprintf(nlfile,"LIBRARY %s;\n",EXTLIBNAME);
	// Write the design interface
	fprintf(nlfile,"ENTITY top IS\n");
	fprintf(nlfile,"  PORT (\n");
	// Scan the port list
	forall (cnet where strmatch(cnet.NAME,PORTPATT)!=0) {
		// Get the port name
		netname=strextract(cnet.NAME,4,strlen(cnet.NAME));
		convnetname(netname);
		// Scan the port type
		inoutfound=outfound=0;
		forall (cpin of cnet)
			forall (attr of cpin where attr.NAME==PINDIRATT) {
				// Get the direction
				dirname=attr.VALUE;
				strupper(dirname);
				if (dirname=="INOUT")
					inoutfound=1;
				else if (dirname=="OUTPUT")
					outfound=1;
				break;
				}
		// Output the port type
		if (inoutfound) {
			iol[ion]=netname;
			ion++;
			}
		else if (outfound) {
			outl[outn]=netname;
			outn++;
			}
		else {
			inpl[inpn]=netname;
			inpn++;
			}
		}
	// Write inputs
	if (inpn) {
		for (i=0;i<inpn;i++)
			fprintf(nlfile,"%s%s",i==0 ? "       " : ", ",inpl[i]);
		fprintf(nlfile," : IN bit");
		listflag=1;
		}
	// Write output
	if (outn) {
		if (listflag)
			fprintf(nlfile,";\n");
		else
			listflag=1;
		for (i=0;i<outn;i++)
			fprintf(nlfile,"%s%s",i==0 ? "       " : ", ",outl[i]);
		fprintf(nlfile," : OUT bit");
		}
	// Write bidirectionals
	if (ion) {
		if (listflag)
			fprintf(nlfile,";\n");
		else
			listflag=1;
		for (i=0;i<ion;i++)
			fprintf(nlfile,"%s%s",i==0 ? "       " : ", ",iol[i]);
		fprintf(nlfile," : INOUT bit");
		}
	fprintf(nlfile,");\n");
	fprintf(nlfile,"END top;\n\n");
	fprintf(nlfile,"ARCHITECTURE structural OF top IS\n");
	// Scan the port list
	listflag=0;
	forall (cnet where strmatch(cnet.NAME,PORTPATT)==0) {
		// Get the port name
		netname=cnet.NAME;
		convnetname(netname);
		if (netname[0]=='\'')
			continue;
		if (listflag) {
			fprintf(nlfile,",\n");
			}
		else {
			fprintf(nlfile,"   SIGNAL\n");
			listflag=1;
			}
		fprintf(nlfile,"      %s",netname);
		}
	if (listflag)
		fprintf(nlfile,"       : bit ;\n");
	for (i=0;i<lpartn;i++) {
		fprintf(nlfile,"   COMPONENT %s\n",lpartl[i].llname);
		fprintf(nlfile,"      PORT (\n");
		// Write inputs
		if (lpartl[i].inpn) {
			for (j=0;j<lpartl[i].inpn;j++)
				fprintf(nlfile,"%s%s",j==0 ?
				 "             " : ", ",lpartl[i].inpl[j]);
			fprintf(nlfile," : IN bit");
			listflag=1;
			}
		// Write output
		if (lpartl[i].outn) {
			if (listflag)
				fprintf(nlfile,";\n");
			else
				listflag=1;
			for (j=0;j<lpartl[i].outn;j++)
				fprintf(nlfile,"%s%s",
				 j==0 ? "             " : ", ",lpartl[i].outl[j]);
			fprintf(nlfile," : OUT bit");
			}
		// Write bidirectionals
		if (lpartl[i].ion) {
			if (listflag)
				fprintf(nlfile,";\n");
			else
				listflag=1;
			for (j=0;j<lpartl[i].ion;j++)
				fprintf(nlfile,"%s%s",
				 j==0 ? "       " : ", ",lpartl[i].iol[j]);
			fprintf(nlfile," : INOUT bit");
			}
		fprintf(nlfile,"      );\n");
		fprintf(nlfile,"   END COMPONENT;\n");
		}
	fprintf(nlfile,"BEGIN\n");
	// Write the part list
	forall (cpart) {
		partname=cpart.NAME;
		// Get the logical library part name
		forall (attr of cpart where attr.NAME=="$llname") {
			// Store the logical library part name
			logname=attr.VALUE;
			break;
			}
		fprintf(nlfile,"   %s : %s\n",partname,logname);
		fprintf(nlfile,"      PORT MAP (");
		listflag=0;
		forall (cpin of cpart) {
			// Get the net name
			netname=cpin.CNET.NAME;
			// Check if port net
			if (strmatch(netname,PORTPATT)!=0) {
				// Get the port name
				netname=strextract(netname,4,strlen(netname));
				// Convert and store it
				convnetname(netname);
				}
			else {
				// Convert the net name
				convnetname(netname);
				}
			fprintf(nlfile,"%s%s => %s",
			 listflag ? ",\n         " : "\n         ",
			 cpin.NAME,netname);
			listflag=1;
			}
		fprintf(nlfile,"\n         );\n");
		}
	fprintf(nlfile,"END structural;\n\n");
	fprintf(nlfile,"CONFIGURATION top_config OF top IS\n");
	fprintf(nlfile,"   FOR structural\n");
	for (i=0;i<lpartn;i++) {
		fprintf(nlfile,"      FOR ALL : %s\n",lpartl[i].llname);
		fprintf(nlfile,"         USE ENTITY %s.%s (behavioral);\n",
		 EXTLIBNAME=="" ? "work" : EXTLIBNAME,lpartl[i].llname);
		fprintf(nlfile,"      END FOR;\n");
		}
	fprintf(nlfile,"   END FOR;\n");
	fprintf(nlfile,"END top_config;\n");
}

static void convnetname(string netname)
/*
// Convert the net name to VHDL
*/
{
	int len;		// Net name string length
	int i;			// Loop control variable
	// Replace gnd and vcc with constants
	if (netname=="vss" || netname=="gnd") {
		netname="'0'";
		return;
		}
	if (netname=="vdd" || netname=="vcc") {
		netname="'1'";
		return;
		}
	// Replace the first char. of a numeric net name
	if (netname[0]=='@') {
		netname[0]='_';
		netname="local"+netname;
		}
	// Determine the net name length
	len=strlen(netname);
	// Replace all bus dot characters
	for (i=0;i<len;i++)
		if (netname[i]=='.')
			netname[i]='_';
	// Convert all net names to lowercase
	strlower(netname);
}

string getdatetime()
/*
// Get current date and time string
// Return value :
//	date time string
*/
{
	string datetime			/* Date time string */;
	int sec,min,hour		/* Time values */;
	int day,month,year		/* Date values */;
	int weekday,yearday		/* Day values */;
	string dname,mname		/* Day name, month name */;
	// Get date and time
	localtime(sec,min,hour,day,month,year,weekday,yearday);
	// Get the weekday name
	switch (weekday) {
		case 0 : dname="Sun"; break;
		case 1 : dname="Mon"; break;
		case 2 : dname="Tue"; break;
		case 3 : dname="Wed"; break;
		case 4 : dname="Thu"; break;
		case 5 : dname="Fri"; break;
		case 6 : dname="Sat"; break;
		}
	// Get the month name
	switch (month) {
		case  0 : mname="Jan"; break;
		case  1 : mname="Feb"; break;
		case  2 : mname="Mar"; break;
		case  3 : mname="Apr"; break;
		case  4 : mname="May"; break;
		case  5 : mname="Jun"; break;
		case  6 : mname="Jul"; break;
		case  7 : mname="Aug"; break;
		case  8 : mname="Sep"; break;
		case  9 : mname="Oct"; break;
		case 10 : mname="Nov"; break;
		case 11 : mname="Dec"; break;
		}
	// Build the date time string
	sprintf(datetime,"%s %s %d %02d:%02d:%02d %d",
	 dname,mname,day,hour,min,sec,1900+year);
	// Return the date time string
	return(datetime);
}

// User Language program end